1. Field of the Invention
The present invention generally relates to a clock recovery apparatus that generates a recovery clock for receiving data from received data.
Priority is claimed on Japanese Patent Application No. 2007-49027, filed Feb. 28, 2007, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
FIG. 5 is a block diagram illustrating the configuration of a conventional clock recovery apparatus. A conventional clock recovery apparatus 100 includes a first oscillator 101, a second oscillator 102, an inverter circuit 103, an OR-gate 104, a D-flip-flop 105, and a frequency controller 106. The first oscillator 101 has a reset terminal Reset that receives an input of received data D101. The inverter circuit 103 receives the input of received data D101 and generates the inverted data. The second oscillator 102 is placed in parallel to the first oscillator 101. The second oscillator 102 has a reset terminal Reset that receives the inverted data from the inverter circuit 103.
The first oscillator 101 is configured to generate a first output signal having a predetermined first frequency from an output terminal Q when the received data D101 is high-level (H). The first oscillator 101 is configured to discontinue oscillation when the received data D101 is low-level (L). The second oscillator 102 is configured to generate a second output signal having a predetermined second frequency from an output terminal Q when the received data D101 is low-level (L). The second oscillator 102 is configured to discontinue oscillation when the received data D101 is high-level (H).
The OR-gate 104 has first and second input terminals that are connected to the outputs Q of the first and second oscillators 101 and 102. The OR-gate 104 receives the first and second output signals from the first and second oscillators 101 and 102. The OR-gate 104 performs a logic-OR operation of the first and second output signals from the first and second oscillators 101 and 102, and generates a recovery clock CK101 as the result of the logic-OR operation. The recovery clock CK101 is synchronized with the received data D101.
The D-flip-flop 105 has a D-input terminal that receives the received data D101. The D-flip-flop 105 has a clock terminal that receives the recovery clock CK101 from the output of the OR-gate 104. The D-flip-flop 105 generates a recovery data D102 from the received data D101 and the recovery clock CK101. The frequency controller 106 receives the first and second output signals from the first and second oscillators 101 and 102 and a reference clock signal RC101. The frequency controller 106 controls oscillation frequencies of the first and second oscillators 101 and 102 based on the three input signals, for example, the first and second output signals from the first and second oscillators 101 and 102 and the reference clock signal RC101. The frequency controller 106 controls oscillation frequencies of the first and second oscillators 101 and 102 so that the first and second output signals from the first and second oscillators 101 and 102 have the same frequency.
Operations of the conventional clock recovery apparatus 100 will be described, assuming that the first and second output signals from the first and second oscillators 101 and 102 have the same frequency. Detailed descriptions of the control by the frequency controller 106 will be omitted.
The received data D101 is input into the clock recovery apparatus 100. The received data D101 is input into the reset terminal of the first oscillator 101. The received data D101 is input into the inverter circuit 103. The received data D101 is inverted into the inverted data by the inverter circuit 103. The inverted data is then input into the reset terminal Reset of the second oscillator 102. When the received data D101 is high-level (H), the first oscillator 101 generates the first output signal having the predetermined first frequency from the output terminal Q, while the second oscillator 102 discontinues oscillation. The first output signal having the predetermined first frequency from the output terminal Q of the first oscillator 101 is input into the first input terminal of the OR-gate 104. When the received data D101 is low-level (L), the second oscillator 102 generates the second output signal having the predetermined second frequency from the output terminal Q, while the first oscillator 101 discontinues oscillation. The second output signal having the predetermined second frequency from the output terminal Q of the second oscillator 102 is input into the second input terminal of the OR-gate 104. The OR-gate 104 generates the recovery clock CK101 as the result of the logic-OR operation. The received data D101 and the recovery clock CK101 are input into the D-flip-flop 105. The D-flip-flop 105 outputs the recovery data D102.
As described above, the conventional clock recovery apparatus 100 allows the first and second oscillators 101 and 102 to perform selective operation in accordance with the level of the received data D101, thereby continuously generating the recovery clock CK101.
The details of the above-described conventional clock recovery apparatus 100 is disclosed by Yusuke Ota, Robert G. Swartz, Vance D. Archer, Steven K. Korotky, Mihai Banu, Alfred E. Dunlop, “High Speed, Burst-Mode, Packet-Capable Optical Receiver and Instantaneous Clock Recovery for Optical Bus Operation” Journal of Lightwave Technology, February 1994, vol. 12, No. 2, p-325.
In recent years, a high speed optical communication line such as Synchronous Optical NETwork/Synchronous Digital Hierarchy (SONET/SDH), in order to realize higher transmission speed and larger channel capacity. In some cases, Ethernet can be used as a local area network. Ethernet of 1 Gbps or more has been wide-spread. Such high speed communication line needs a clock recovery apparatus that is capable of generating recovery clock stably for high bit rate data.
The conventional clock recovery apparatus 100 is configured to selectively operate the first and second oscillators 101 and 102 in accordance with the level of the received data D101, wherein the first and second oscillators 101 and 102 are connected in parallel to each other with reference to the input into which the received data D101 is input. A difference in the delay time between the first and second oscillators 101 and 102 deteriorates the stability of high speed performance of the conventional clock recovery apparatus 100. The difference in the delay time between the first and second oscillators 101 and 102 may cause that the first and second oscillators 101 and 102 output the first and second output signals simultaneously at a time of switching one to another of the first and second oscillators 101 and 102. The first and second output signals that have been simultaneously output from the first and second oscillators 101 and 102 are input into the OR-gate 104. The recovery clock CK101 output from the OR-gate 104 has a part having a longer frequency. An error may occur on the recovery data D102 that is output from the D-flip-flop 105.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved clock recovery apparatus. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.